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general description the MAX5858A dual, 10-bit, 300msps digital-to-analog converter (dac) provides superior dynamic performance in wideband communication systems. the MAX5858A integrates two 10-bit dac cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (pll) clock multiplier, and a 1.24v reference. the MAX5858A sup- ports single-ended and differential modes of operation. the MAX5858A dynamic performance is maintained over the entire power-supply operating range of 2.7v to 3.3v. the analog outputs support a compliance voltage of -1.0v to +1.25v. the 4x/2x/1x programmable interpolation filters feature excellent passband distortion and noise performance. interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and the clock speeds of the digital interface. the pll multiplier generates all internal, synchronized high- speed clock signals for interpolating filter operation and dac core conversion. the internal pll helps minimize system complexity and lower cost. to reduce the i/o pin count, the dac can also operate in interleave data mode. this allows the MAX5858A to be updated on a single 10-bit bus. the MAX5858A features digital control of channel gain matching to within ?.4db in sixteen 0.05db steps. channel matching improves sideband suppression in analog quadrature modulation applications. the on- chip 1.24v bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. the internal ref- erence can be disabled and an external reference can be applied for high-accuracy applications. the MAX5858A features full-scale current outputs of 2ma to 20ma and operates from a 2.7v to 3.3v single supply. the dac supports three modes of power-con- trol operation: normal, low-power standby, and com- plete power-down. in power-down mode, the operating current is reduced to 1?. the MAX5858A is packaged in a 48-pin tqfp with exposed paddle (ep) for enhanced thermal dissipation and is specified for the extended (-40? to +85?) opera- ting temperature range. applications communications satcom, lmds, mmds, hfc, dsl, wlan, point-to-point microwave links wireless base stations direct digital synthesis instrumentation/ate features 10-bit resolution, dual dac 300msps update rate integrated 4x/2x/1x interpolating filters internal pll multiplier 2.7v to 3.3v single supply full output swing and dynamic performance at 2.7v supply superior dynamic performance 73dbc sfdr at f out = 20mhz umts aclr = 63db at f out = 30.7mhz programmable channel gain matching integrated 1.24v low-noise bandgap reference single-resistor gain control interleave data mode differential clock input modes ev kit available?ax5858aevkit MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ________________________________________________________________ maxim integrated products 1 ordering information 19-2999; rev 0; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX5858Aecm -40 c to +85 c 48 tqfp-ep* da9/pd da8/dacen da7/f2en da3/g1 da4/g2 note: exposed paddle connected to gnd. dv dd dgnd da5/g3 da6/f1en da2/g0 dv dd dgnd ide clk db4 pgnd pv dd clkxn clkxp pllen lock pllf refo refr dv dd outna agnd outpb outnb av dd dgnd av dd outpa db2 da0 db1 n.c. n.c. db0 db3 db5 db6 db7 db8 db9 da1 tqfp-ep ren cw 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 ep 42 41 40 39 38 37 MAX5858A pin configuration * ep = exposed paddle.
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, f dac = 165msps, no interpolation, pll disabled, external reference, v refo = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a > +25 c guaranteed by production test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , dv dd , pv dd to agnd, dgnd, pgnd ..........-0.3v to +4v da9 da0, db9 db0, cw , ren, pllf, pllen to agnd, dgnd, pgnd........................................................-0.3v to +4v ide to agnd, dgnd, pgnd ...................-0.3v to (dv dd + 0.3v) clkxn, clkxp to pgnd .........................................-0.3v to +4v outp_, outn_ to agnd.......................-1.25v to (av dd + 0.3v) clk, lock to dgnd...............................-0.3v to (dv dd + 0.3v) refr, refo to agnd .............................-0.3v to (av dd + 0.3v) agnd to dgnd, dgnd to pgnd, agnd to pgnd ..................................................-0.3v to +0.3v maximum current into any pin (excluding power supplies) ............................................50ma continuous power dissipation (t a = +70 c) 48-pin tqfp-ep (derate 36.2mw/ c above +70 c) ....2.899w operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units static performance resolution 10 bits integral nonlinearity inl r l = 0 -1.25 0.5 +1.25 lsb differential nonlinearity dnl guaranteed monotonic, r l = 0 -0.75 0.25 +0.75 lsb offset error v os -0.5 0.1 +0.5 lsb internal reference (note 1) -10 1.6 +11 gain error (see gain error parameter definitions section) ge external reference -8 1.2 +8 % dynamic performance maximum dac update rate f dac 4x/2x interpolation modes 300 msps glitch impulse 5 pv-s f out = 5mhz, t a +25 c 68 76 f out = 20mhz 73 f out = 50mhz 66 f dac = 165msps f out = 70mhz 65 f out = 5mhz 76 f out = 40mhz 73 spurious-free dynamic range to input update rate nyquist sfdr f dac = 300msps, 2x interpolation f out = 60mhz 72 dbc f dac = 200msps, 2x interpolation, f out = 40mhz, span = 20mhz 85 spurious-free dynamic range within a window sfdr f dac = 165msps, f out = 5mhz, span = 4mhz 76.5 85 dbc multitone power ratio, 8 tones, ~300khz spacing mtpr f dac = 165msps, f out = 20mhz 76 dbc adjacent channel leakage ratio with umts aclr f dac =122.88msps, f out = 30.72mhz 63 db
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, f dac = 165msps, no interpolation, pll disabled, external reference, v refo = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a > +25 c guaranteed by production test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units total harmonic distortion to nyquist thd f dac = 165msps, f out = 5mhz -72 dbc noise spectral density n d f dac = 165msps, f out = 5mhz -143 dbm/hz output channel-to-channel isolation f out = 5mhz 80 db gain mismatch between channels f out = 5mhz 0.05 db phase mismatch between channels f out = 5mhz 0.15 degrees wideband output noise 50 pa/ hz analog output full-scale output current range i fs 220ma output voltage compliance range -1.0 +1.25 v output leakage current power-down or standby mode -5 +5 a reference reference output voltage v ref0 ren = agnd 1.14 1.24 1.34 v output-voltage temperature drift tcv ref 50 ppm/ c reference output drive capability 50 a reference input voltage range ren = av dd 0.10 1.32 v reference supply rejection 0.2 mv/v current gain i fs /i ref 32 ma/ma interpolation filter (2x interpolation) -0.005db 0.398 -0.01db 0.402 -0.1db 0.419 passband width f out / 0.5f dac -3db 0.478 mhz/ mhz 0.604f dac / 2 to 1.396f dac / 2 74 0.600f dac / 2 to 1.400f dac / 2 62 0.594f dac / 2 to 1.406f dac / 2 53 stopband rejection 0.532f dac / 2 to 1.468f dac / 2 14 db group delay 18 data clock cycles impulse response duration 22 data clock cycles
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, f dac = 165msps, no interpolation, pll disabled, external reference, v refo = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a > +25 c guaranteed by production test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units interpolation filter (4x interpolation) -0.005db 0.200 -0.01db 0.201 -0.1db 0.210 passband width f out / 0.5f dac -3db 0.239 mhz/ mhz 0.302f dac / 2 to 1.698f dac / 2 74 0.300f dac / 2 to 1.700f dac / 2 63 0.297f dac / 2 to 1.703 f dac / 2 53 stopband rejection 0.266f dac / 2 to 1.734f dac / 2 14 db group delay 22 data clock cycles impulse response duration 27 data clock cycles logic inputs (ide, cw , ren , da9 da0, db9 db0, pllen) digital input-voltage high v ih 2v digital input-voltage low v il 0.8 v digital input-current high i h v ih = 2v -1 +1 a digital input-current low i il v il = 0.8v -1 +1 a digital input capacitance c in 3pf digital outputs (clk, lock) digital output-voltage high v oh i source = 0.5ma, figure 1 0.9 dv dd v digital output-voltage low v ol i sink = 0.5ma, figure 1 0.1 dv dd v differential clock input (clkxp, clkxn) clock input internal bias pv dd / 2 v differential clock input swing 0.5 v p-p clock input impedance single-ended clock drive 5 k ? timing characteristics no interpolation 165 pll disabled 150 2x interpolation pll enabled 75 150 pll disabled 75 input data rate f data 4x interpolation pll enabled 37.5 75 msps no interpolation, pll enabled 165 2x interpolation, pll enabled 75 150 clock frequency at clk input f clk 4x interpolation, pll enabled 37.5 75 mhz
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, f dac = 165msps, no interpolation, pll disabled, external reference, v refo = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a > +25 c guaranteed by production test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units output settling time t s to 0.1% error band (note 2) 11 ns output rise time 10% to 90% (note 2) 2.5 ns output fall time 90% to 10% (note 2) 2.5 ns pll disabled 1.5 data-to-clk rise setup time (note 3) t dcsr pll enabled 2.2 ns pll disabled 0.4 data-to-clk rise hold time (note 3) t dchr pll enabled 1.4 ns pll disabled 1.8 data-to-clk fall setup time (note 3) t dcsf pll enabled 2.4 ns pll disabled 1.2 data-to-clk fall hold time (note 3) t dchf pll enabled 1.3 ns control word to cw fall setup time t cws 2.5 ns control word to cw fall hold time t cwh 2.5 ns cw high time 5ns cw low time 5ns dacen rise-to-v out stable t stb 0.7 s pd fall-to-v out stable t pdstb external reference 0.5 ms clock frequency at clkxp/clkxn input f clkdiff differential clock, pll disabled 300 mhz clkxp/clkxn differential clock input to clk output delay t cxd pll disabled 4.6 ns minimum clkxp/clkxn clock high time t cxh 1.5 ns minimum clkxp/clkxn clock low time t cxl 1.5 ns power requirements analog power-supply voltage av dd 2.7 3.3 v analog supply current i avdd (note 4) 45 49 ma digital power-supply voltage dv dd 2.7 3.3 v
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 6 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, f dac = 165msps, no interpolation, pll disabled, external reference, v refo = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a > +25 c guaranteed by production test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units no interpolation 34 2x interpolation 75 f dac = 60msps 4x interpolation 72 no interpolation 54 61 2x interpolation 146 f dac = 165msps 4x interpolation 140 2x interpolation 172 186 digital supply current (note 4) i dvdd f dac = 200msps 4x interpolation 165 178 ma pll power-supply voltage pv dd 2.7 3.3 v f dac = 60msps 17 f dac = 165msps 46 52 pll supply current (note 4) i pvdd f dac = 200msps, 2x interpolation or 4x interpolation 55 61 ma standby current i standby (note 5) 4.4 4.8 ma power-down current i pd (note 5) 1 a no interpolation 324 2x interpolation 487 f dac = 60msps 4x interpolation 498 no interpolation 438 486 2x interpolation 735 f dac = 165msps 4x interpolation 721 2x interpolation 816 total power dissipation (note 4) p tot f dac = 200msps 4x interpolation 795 mw note 1: including the internal reference voltage tolerance. note 2: measured single ended with 50 ? load and complementary output connected to ground. note 3: guaranteed by design, not production tested. note 4: tested with an output frequency of f out = 5mhz. note 5: all digital inputs at 0 or dv dd . clock signal disabled. to output pin 5pf 0.5ma 0.5ma 1.6v figure 1. load test circuit for clk outputs
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll _______________________________________________________________________________________ 7 0 40 30 20 10 60 50 80 70 90 100 0 102030405060708090 spurious-free dynamic range vs. output frequency (no interpolation, f dac = 165mhz) MAX5858A toc01 output frequency (mhz) sfdr (dbc) a out = -6dbfs a out = -12dbs pll disabled a out = 0dbfs 0 40 30 20 10 60 50 80 70 90 100 035 spurious-free dynamic range vs. output frequency (no interpolation, f dac = 65mhz) MAX5858A toc02 output frequency (mhz) sfdr (dbc) 20 15 10 530 25 a out = 0dbfs a out = -6dbfs a out = -12dbfs pll disabled 0 40 30 20 10 60 50 80 70 90 100 080 spurious-free dynamic range vs. output frequency (2x interpolation, f dac = 300mhz) MAX5858A toc03 output frequency (mhz) sfdr (dbc) 40 30 20 10 70 60 50 a out = 0dbfs a out = -6dbfs a out = -12dbfs pll disabled 0 40 30 20 10 60 50 80 70 90 100 080 spurious-free dynamic range vs. output frequency (2x interpolation, f dac = 300mhz) MAX5858A toc04 output frequency (mhz) sfdr (dbc) 40 30 20 10 70 60 50 a out = -12dbfs a out = -6dbfs a out = 0dbfs pll enabled 045 spurious-free dynamic range vs. output frequency (2x interpolation, f dac = 165mhz) MAX5858A toc05 output frequency (mhz) sfdr (dbc) 20 15 10 540 35 30 25 pll disabled 0 40 30 20 10 60 50 80 70 90 100 a out = 0dbfs a out = -6dbfs a out = -12dbfs 0 40 30 20 10 60 50 80 70 90 100 0369 12 15 18 21 spurious-free dynamic range vs. output frequency (4x interpolation, f dac = 165mhz) MAX5858A toc06 output frequency (mhz) sfdr (dbc) pll disabled a out = -6dbfs a out = -12dbfs a out = 0dbfs 0 40 30 20 10 60 50 80 70 90 100 040 spurious-free dynamic range vs. output frequency (4x interpolation, f dac = 300mhz) MAX5858A toc07 output frequency (mhz) sfdr (dbc) 20 15 10 535 30 25 a out = -6dbfs a out = 0dbfs a out = -12dbfs pll enabled 0 40 30 20 10 60 50 80 70 90 100 040 spurious-free dynamic range vs. output frequency (4x interpolation, f dac = 300mhz) MAX5858A toc08 output frequency ( mhz ) sfdr (dbc) 20 15 10 535 30 25 a out = -6dbfs a out = 0dbfs a out = -12dbfs pll disabled typical operating characteristics (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, external reference = 1.2v, no interpolation, pll disabled, i fs = 20ma, differential output, t a = +25 c, unless otherwise noted.)
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 8 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, external reference = 1.2v, no interpolation, pll disabled, i fs = 20ma, differential output, t a = +25 c, unless otherwise noted.) spurious-free dynamic range vs. output frequency (no interpolation, f dac = 165mhz) MAX5858A toc10 output frequency (mhz) sfdr (dbc) 80 70 50 60 20 30 40 10 10 20 30 40 50 60 70 80 90 100 0 090 t a = -10 c t a = +25 c t a = +85 c -100 -60 -70 -80 -90 -40 -50 -20 -30 -10 0 7.8 11.4 fft plot ( 2mhz window) MAX5858A toc11 output frequency (mhz) output power (dbm) 9.4 9.0 8.6 8.2 11.0 10.6 10.2 9.8 f dac = 165mhz f out = 10mhz a out = -6dbfs -100 -60 -70 -80 -90 -40 -50 -20 -30 -10 0 0 8.25 16.50 24.75 33.00 41.25 49.50 57.75 66.00 74.25 82.50 fft plot for dac update nyquist window (no interpolation, f dac = 165mhz, f out = 10mhz, a out = 0dbfs) MAX5858A toc12 output frequency (mhz) output power (dbm) 0 102030405060708090100 fft plot for dac update nyquist window (2x interpolation, f dac = 200mhz, f out = 10mhz, a out = 0dbfs) MAX5858A toc13 output frequency (mhz) output power (dbm) -100 -60 -70 -80 -90 -40 -50 -20 -30 -10 0 0 102030405060708090100 fft plot for dac update nyquist window (4x interpolation, f dac = 200mhz, f out = 10mhz, a out = 0dbfs) MAX5858A toc14 output frequency (mhz) output power (dbm) -100 -60 -70 -80 -90 -40 -50 -20 -30 -10 0 spurious-free dynamic range vs. temperature (no interpolation, f dac = 165mhz, f out = 5mhz) MAX5858A toc09 temperature ( c) sfdr (dbc) 60 35 10 -15 10 20 30 40 50 60 70 80 90 100 0 -40 85 a out = -12dbfs a out = -6dbfs a out = 0dbfs
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll _______________________________________________________________________________________ 9 typical operating characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, external reference = 1.2v, no interpolation, pll disabled, i fs = 20ma, differential output, t a = +25 c, unless otherwise noted.) -100 -30 -40 -10 -20 -70 -80 -90 -50 -60 0 4.5 4.7 4.9 5.1 5.3 5.5 2-tone imd plot (no interpolation, f dac = 165mhz) MAX5858A toc15 output frequency (mhz) output power (dbm) a out = -6dbfs bw = 1mhz f t1 = 4.9448mhz f t2 = 5.0656mhz 2 x f t1 - f t2 f t1 f t2 2 x f t2 - f t1 -100 -30 -40 -10 -20 -70 -80 -90 -50 -60 0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 8-tone mtpr plot (no interpolation, f dac = 165mhz, f center = 19.9503mhz) output frequency (mhz) output power (dbm) MAX5858A toc16 a out = -18db fs bw = 3mhz f t1 = 18.8022mhz f t5 = 20.2524mhz f t2 = 19.0237mhz f t6 = 20.5344mhz f t3 = 19.2654mhz f t7 = 20.8365mhz f t4 = 19.6481mhz f t8 = 21.1386mhz f t4 f t5 f t1 f t2 f t3 f t6 f t7 f t8 -100 -30 -40 -10 -20 -70 -80 -90 -50 -60 0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 8-tone mtpr plot (4x interpolation, f dac = 286.4mhz, f center = 29.9572mhz) MAX5858A toc17 output frequency (mhz) output power (dbm) a out = -18dbfs bw = 3mhz f t1 = 28.7597mhz f t5 = 30.2281mhz f t2 = 29.1008mhz f t6 = 30.5952mhz f t3 = 29.3628mhz f t7 = 30.8924mhz f t4 = 29.6862mhz f t8 = 31.1546mhz f t4 f t5 f t1 f t2 f t3 f t6 f t7 f t8 -100 -30 -40 -20 -10 -70 -80 -90 -60 -50 -1 1.00 9.15 17.30 25.25 33.60 41.75 49.90 58.05 66.20 74.35 82.50 8-tone mtpr plot for nyquist window (no interpolation, f dac = 165mhz, f center = 19.9569mhz, a out = -18dbfs) MAX5858A toc18 output frequency (mhz) output power (dbm) mtpr = 76dbc -100 -40 -50 -30 -20 -80 -90 -70 -60 0 -10 1.0 15.2 28.6 42.9 57.2 71.5 85.8 100.1 114.4 128.7 143.2 8-tone mtpr plot for nyquist window (4x interpolation, f dac = 286.4mhz, f center = 20mhz, input tones spacing ~ 300khz, a out = -18dbfs) MAX5858A toc19 output frequency (mhz) output power (dbm) a b 35.8mhz a: in-band-range b: out-of-band range -30 -40 -50 -60 -70 -80 -90 -100 -10 -20 0 61.44 aclr umts plot (no interpolation, f dac = 122.88mhz, f data = 122.88mhz, f center = 30.72mhz) MAX5858A toc20 6.14mhz/div output power (dbm) output frequency (mhz) aclr = 63db
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 10 ______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, external reference = 1.2v, no interpolation, pll disabled, i fs = 20ma, differential output, t a = +25 c, unless otherwise noted.) -30 -40 -50 -60 -70 -80 -90 -100 -0 -10 -20 0 122.88 aclr with umts plot (no interpolation, f dac = 122.88mhz, f data = 122.88mhz, f center = 30.72mhz) MAX5858A toc21 output frequency (mhz) output power (dbm) 12.288mhz/div aclr = 63db 0 61.44 aclr with umts plot (2x interpolation, f dac = 245.76mhz, f data = 122.88mhz, f center = 30.72mhz) MAX5858A toc22 output frequency (mhz) output power (dbm) 6.14mhz/div -30 -40 -50 -60 -70 -80 -90 -100 -0 -10 -20 aclr = 63db 0 122.88 aclr with umts plot (2x interpolation, f dac = 245.76mhz, f data = 122.88mhz, f center = 30.72mhz) MAX5858A toc23 output frequency (mhz) output power (dbm) 12.288mhz/div -30 -40 -50 -60 -70 -80 -90 -100 -0 -10 -20 aclr = 63db fft plot for pll disabled and pll enabled (f out = 10mhz, 2x interpolation) MAX5858A toc24 output frequency (mhz) output power (dbm) 1mhz/div 515 -30 -20 -10 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 pll enabled pll disabled phase noise with pll disabled and enabled (f out = f data /4, 2x interpolation) MAX5858A toc25 offset frequency (mhz) noise density (dbm/hz) 0.5mhz/div 0 5 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -30 pll enabled f data = 125mhz pll enabled f data = 100mhz pll enabled f data = 150mhz pll disabled f data = 75mhz -0.5 -0.2 -0.3 -0.4 0 -0.1 0.4 0.3 0.2 0.1 0.5 0 150 300 450 600 750 900 1050 integral nonlinearity vs. digital input code MAX5858A toc26 digital input code inl (lsb) r l = 0
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ______________________________________________________________________________________ 11 typical operating characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, external reference = 1.2v, no interpolation, pll disabled, i fs = 20ma, differential output, t a = +25 c, unless otherwise noted.) -0.30 -0.10 -0.20 0 0.20 0.10 0.30 0 150 300 450 600 750 900 1050 differential nonlinearity vs. digital input code MAX5858A toc27 digital input code inl (lsb) r l = 0 200 300 250 400 350 450 0 165 power dissipation vs. f dac MAX5858A toc28 f dac (mhz) power dissipation (mw) 68 34 102 136 f out = 5mhz no interpolation 350 550 450 950 750 850 650 1050 0 300 power dissipation vs. f dac MAX5858A toc28 f dac (mhz) power dissipation (mw) 150 100 50 200 250 4x interpolation 2x interpolation power dissipation vs. supply voltage MAX5858A toc30 supply voltage (v) power dissipation (mw) 3.2 3.1 2.8 2.9 3.0 300 400 500 600 700 800 900 1000 200 2.7 3.3 2x interpolation f clk = 200mhz f out = 5mhz no interpolation f clk = 165mhz f out = 5mhz 4x interpolation f clk = 200mhz f out = 5mhz 1.20 1.22 1.21 1.24 1.23 1.26 1.25 1.27 1.28 2.7 3.3 3.2 internal reference voltage vs. supply voltage MAX5858A toc31 supply voltage (v) internal reference voltage (v) 2.9 2.8 3.0 3.1 1.20 1.22 1.21 1.24 1.23 1.26 1.25 1.27 1.28 -40 85 internal reference voltage vs. temperature MAX5858A toc32 temperature ( c) internal reference voltage (v) 10 -15 35 60
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 12 ______________________________________________________________________________________ pin description typical operating characteristics (continued) (av dd = dv dd = pv dd = 3v, agnd = dgnd = pgnd = 0, external reference = 1.2v, no interpolation, pll disabled, i fs = 20ma, differential output, t a = +25 c, unless otherwise noted.) pin name function 1 da9/pd channel a input data bit 9 (msb)/power-down control bit: 0: enter dac standby mode (dacen = 0) or power up dac (dacen = 1). 1: enter power-down mode. 2 da8/dacen channel a input data bit 8/dac enable control bit: 0: enter dac standby mode with pd = 0. 1: power up dac with pd = 0. x: enter power-down mode with pd = 1 (x = don t care.) 3 da7/f2en channel a input data bit 7/second interpolation filter enable bit: 0: interpolation mode is determined by f1en. 1: enable 4x interpolation mode. (f1en must equal 1.) 4 da6/f1en channel a input data bit 6/first interpolation filter enable bit: 0: interpolation disable. 1: enable 2x interpolation. 5 da5/g3 channel a input data bit 5/channel a gain adjustment bit 3 6, 19, 47 dgnd digital ground 7, 18, 48 dv dd digital power supply. see power supplies, bypassing, decoupling, and layout section. 8 da4/g2 channel a input data bit 4/channel a gain adjustment bit 2 9 da3/g1 channel a input data bit 3/channel a gain adjustment bit 1 10 da2/g0 channel a input data bit 2/channel a gain adjustment bit 0 11 da1 channel a input data bit 1 12 da0 channel a input data bit 0 (lsb) dynamic response rise time MAX5858A toc33 10ns/div 200mv/div r l = 50 ? single ended dynamic response fall time MAX5858A toc34 10ns/div r l = 50 ? single ended 200mv/div
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ______________________________________________________________________________________ 13 pin description (continued) pin name function 13 db9 channel b input data bit 9 (msb) 14 db8 channel b input data bit 8 15 db7 channel b input data bit 7 16 db6 channel b input data bit 6 17 db5 channel b input data bit 5 20 clk clock output/input. clk becomes an input when the pll is enabled. clk is an output when the pll is disabled. 21 ide interleave data mode enable. when ide is high, data for both dac channels is written through port a (bits da9 da0). when ide is low, channel a data is latched on the rising edge of clk and channel b data is latched on the falling edge of clk. 22 db4 channel b input data bit 4 23 db3 channel b input data bit 3 24 db2 channel b input data bit 2 25 db1 channel b input data bit 1 26 db0 channel b input data bit 0 (lsb) 27 cw active-low control-word write pulse. the control word is latched on the falling edge of cw . 28 lock pll lock signal output. high level indicates that pll is locked to the clk signal. 29 pllen pll enabled input. pll in enabled when pllen is high. 30 clkxp differential clock input positive terminal. connect to pgnd when the pll is enabled. bypass clkxp with a 0.01f capacitor to pgnd when clkxn is in single-ended mode. 31 clkxn differential clock input negative terminal. connect to pv dd when the pll is enabled. bypass clkxn with a 0.01f capacitor to pgnd when clkxp is in single-ended mode. 32 pv dd pll power supply. see power supplies, bypassing, decoupling, and layout section. 33 pgnd pll ground 34 pllf pll loop filter. connect a 4.12k ? resistor in series with a 100pf capacitor between pllf and pgnd. 35 ren active-low reference enable. connect ren to agnd to activate the on-chip 1.24v reference. 36 refo reference i/o. refo serves as the reference input when the internal reference is disabled. if the internal 1.24v reference is enabled, refo serves as the output for the internal reference. when the internal reference is enabled, bypass refo to agnd with a 0.1f capacitor. 37, 38 n.c. no connection. not connected internally. 39 refr full-scale current adjustment. to set the output full-scale current, connect an external resistor r set between refr and agnd. the output full-scale current is equal to 32 v refo /r set . 40, 46 av dd analog power supply. see power supplies, bypassing, decoupling, and layout section. 41 outnb channel b negative analog current output 42 outpb channel b positive analog current output 43 agnd analog ground 44 outna channel a negative analog current output 45 outpa channel a positive analog current output ep exposed paddle. connect to the ground plane.
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 14 ______________________________________________________________________________________ detailed description the MAX5858A dual, high-speed, 10-bit, current-output dac provides superior performance in communication systems requiring low-distortion analog-signal recon- struction. the MAX5858A combines two dac cores with 2x/4x programmable digital interpolation filters, a pll clock multiplier, divide-by-n clock output, and an on- chip 1.24v reference. the current outputs of the dacs can be configured for differential or single-ended opera- tion. the full-scale output current range is adjustable from 2ma to 20ma to optimize power dissipation and gain control. the MAX5858A accepts an input data rate of up to 165mhz or a dac conversion rate of up to 300mhz. the inputs are latched on the rising edge of the clock where- as the output latches on the following rising edge. the two-stage digital interpolation filters are program- mable to 4x, 2x, or no interpolation. when operating in 4x interpolation mode, the interpolator increases the dac conversion rate by a factor of four, providing a four-fold increase in separation between the recon- structed waveform spectrum and its first image. the on-chip pll clock multiplier generates and distrib- utes all internal, synchronized high-speed clock signals required by the input data latches, interpolation filters, and dac cores. the on-chip pll includes phase-detec- tor, vco, prescalar, and charge-pump circuits. the pll can be enabled or disabled through pllen. the analog and digital sections of the MAX5858A have separate power-supply inputs (av dd and dv dd ). also, a separate supply input is provided for the pll clock multiplier (pv dd ). av dd , dv dd , and pv dd operate from a 2.7v to 3.3v single supply. the MAX5858A features three modes of operation: nor- mal, standby, and power-down. these modes allow effi- cient power management. in power-down, the MAX5858A consumes only 1a of supply current. wake-up time from standby mode to normal dac operation is 0.7s. programming the dac an 8-bit control word routed through channel a s data port programs the gain matching, interpolator configura- tion, and operational mode of the MAX5858A. the con- trol word is latched on the falling edge of cw . table 1 describes the control word format and function. the gain on channel a can be adjusted to achieve gain matching between two channels in a user s system. the gain on channel a can be adjusted from +0.4db to -0.35db in steps of 0.05db by using bits g3 to g0 (see table 3). 2x digital interpolation filter 2x digital interpolation filter input register 10-bit 300mhz dac 10 10 10 10 da9?a0 outpa pllf pllen lock outna 2x digital interpolation filter 2x digital interpolation filter input register 10-bit 300mhz dac 10 10 10 10 db9?b0 outpb outnb control register 1.2v reference and control amplifier pll clock multiplier clk clkxn clkxp f2en f1en agnd refr r set dgnd pgnd refo ren cw ide dv dd pv dd av dd MAX5858A block diagram
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ______________________________________________________________________________________ 15 device power-up and states of operation at power-up, the MAX5858A is configured in no-inter- polation mode with a gain adjustment setting of 0db and a fully operational converter. in shutdown, the MAX5858A consumes only 1a of supply current, and in standby the current consumption is 4.4ma. wake-up time from standby mode to normal operation is 0.7s. interpolation filters the MAX5858A features a two stage, 2x digital interpolat- ing filter based on 43-tap and 23-tap fir topology. f1en and f2en enable the interpolation filters. f1en = 1 enables the first filter for 2x interpolation and f2en = 2 enables the second filter for combined 4x interpolation. to bypass and disable both interpolation filters (no-interpola- tion mode or 1x mode) set f1en = f2en = 0. when set for 1x mode the filters are powered down and consume virtu- ally no current. an illegal condition is defined by: f1en = 0, f2en = 1 (see table 2 for configuration modes). the programmable interpolation filters multiply the MAX5858A input data rate by a factor of two or four to separate the reconstructed waveform spectrum and the first image. the original spectral images, appearing around multiples of the dac input data rate, are attenu- ated at least 60db by the internal digital filters. this fea- ture provides three benefits: 1) image separation reduces complexity of analog reconstruction filters. 2) lower input data rates eliminate board level high- speed data transmission. 3) sin(x)/x roll-off is reduced over the effective band- width. figure 2 shows an application circuit and figure 3 illus- trates a practical example of the benefits when using the MAX5858A with 4x-interpolation mode. the exam- ple illustrates signal synthesis of a 20mhz if with a 10mhz bandwidth. three options can be considered to address the design requirements. the tradeoffs for each solution are depicted in table 4. control word function pd power-down: the part enters power-down mode if pd = 1. dacen dac enable: when dacen = 0 and pd = 0, the part enters standby mode. f2en filter enable: when f2en = 1 and f1en = 1, 4x interpolation is enabled. when f2en = 0, the interpolation mode is determined by f1en. f1en filter enable: when f1en = 1 and f2en = 0, 2x interpolation is active. with f1en = 0 and f2en = 0, the interpolation is disabled. g3 bit 3 (msb) of gain adjust word. g2 bit 2 of gain adjust word. g1 bit 1 of gain adjust word. g0 bit 0 (lsb) of gain adjust word. table 1. control word format and function mode pd dacen f2en f1en no interpolation 010 0 2x interpolation 010 1 4x interpolation 011 1 standby 00x x power-down 1xx x power-up 01x x table 2. configuration modes gain adjustment on channel a (db) g3 g2 g1 g0 +0.4 0000 0 1000 -0.35 1111 table 3. gain difference setting x = don t care. f1en = 0, f2en = 1: illegal condition msb lsb pd dacen f2en f1en g3 g2 g1 g0 x x
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 16 ______________________________________________________________________________________ single 10-bit bus saves i/o pins data clock out f data = 71.6mhz clock source f dac = 286.4mhz interleave data latch data latch 10-bit bus digital baseband ofdm processor qam-mapper fs analog out maintained over entire supply range 2.7v to 3.3v data latch 10-bit bus div-4 div-2 div-1 interpolating filters 4x/2x single supply 2.7v to 3.3v cha dac chb dac bout aout interpolating filters 4x/2x MAX5858A 10 10 figure 2. typical application circuit option solution advantage disadvantage 1 no interpolation 2.6x oversample f dac = f data = 78mhz low data rate low clock rate high order filter filter gain/phase match 2 no interpolation 8x oversample f dac = f data = 240mhz push image to f image = 210mhz lower order filter filter gain/phase match high clock rate high data rate 3 4x interpolation f dac = 286.4mhz, f data = 71.6mhz passband attenuation = 0.1db push image to 256mhz low data rate low order filter 60db image attenuate filter gain/phase match none table 4. benefits of interpolation
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ______________________________________________________________________________________ 17 f out 20mhz 10mhz image f dac - f out 48mhz image f dac + f out 108mhz f dac 78mhz image separation = 18mhz less than one octave high order analog filter solution 1 f out 20mhz bw = 10mhz image f dac - f out 210mhz image f dac + f out 270mhz f dac 240mhz lower order analog filter image separation = 180mhz high-speed clk = 240mhz solution 2 frequency axis not to scale f out 20mhz bw = 10mhz image f dac - f out 256mhz image f dac + f out 316mhz f dac 286mhz f data 71.6mhz simple analog filter new first image separation > 3 octaves solution 3 frequency axis not to scale frequency axis not to scale digital filter attenuation >60db figure 3. MAX5858A in 4x interpolation mode this example demonstrates that 4x interpolation with digital filtering yields significant benefits in reducing sys- tem complexity, improving dynamic performance and lowering cost. data can be written to the MAX5858A at much lower speeds while achieving image attenuation greater than 60db and image separation beyond three octaves. the main benefit is in analog reconstruction fil- ter design. reducing the filter order eases gain/phase matching while lowering filter cost and saving board space. because the data rate is lowered to 71.6mhz, the setup and hold times are manageable and the clock signal source is simplified, which results in improved system reliability and lower cost.
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 18 ______________________________________________________________________________________ i fs c comp * refr i ref refo max4040 1.24v bandgap reference current- source array *compensation capacitor (c comp 100nf). optional external buffer for heavier loads ren MAX5858A i ref = v ref r set r set agnd agnd agnd figure 4. setting ifs with the internal 1.24v reference and the control amplifier pll clock multiplier and clocking modes the MAX5858A features an on-chip pll clock multiplier that generates all internal, synchronized high-speed clock signals required by the input data latches, inter- polation filters, and dac cores. the on-chip pll includes a phase-detector, vco, prescalar, and charge-pump circuits. the pll can be enabled or dis- abled through pllen. to enable pll set pllen = 1. with the pll enabled (pllen = 1) and 4x/2x interpola- tion enabled, an external low-frequency clock reference source is applied to clk pin. the clock reference source serves as the input data clock. the on-chip pll multiplies the clock reference by a factor of two (2x) or a factor of four (4x). the input data rate range and clk frequency are set by the selected interpolation mode. in 2x interpolation mode, the data rate range is 75mhz to 150mhz. in 4x interpolation mode the data rate range is 37.5mhz to 75mhz. note: when the pll is enabled, clk becomes an input, requiring clkxp to be pulled low and clkxn to be pulled high. to obtain best phase noise perfor- mance, disable the pll function. with the pll disabled (pllen = 0) and 4x/2x interpola- tion enabled, an external conversion clock is applied at clkxn/clkxp. the conversion clock at clkxn/clkxp has a frequency range of 0mhz to 300mhz (see table 5). this clock is buffered and distributed by the MAX5858A to drive the interpolation filters and dac cores. in this mode, clk becomes a divide-by-n (div- n) output at either a divide-by-two or divide-by-four rate. the div-n factor is set by the selected interpola- tion mode. the clk output, at div-n rate, must be used to synchronize data into the MAX5858A data ports. in this mode, keep the capacitive load at the clk output low (10pf or less at f dac = 165mhz). with the interpolation disabled (1x mode) and the pll disabled (pllen = 0), the input clock at clkxn/clkxp can be used to directly update the dac cores. in this mode, the maximum data rate is 165mhz. internal reference and control amplifier the MAX5858A provides an integrated 50ppm/ c, 1.24v, low-noise bandgap reference that can be dis- abled and overridden with an external reference volt- age. refo serves either as an external reference input or an integrated reference output. if ren is connected to agnd, the internal reference is selected and refo provides a 1.24v (50a) output. buffer refo with an external amplifier, when driving a heavy load. the MAX5858A also employs a control amplifier designed to simultaneously regulate the full-scale out- put current (i fs ) for both outputs of the devices. calculate the output current as: i fs = 32 ? i ref where i ref is the reference output current (i ref = v refo /r set ) and i fs is the full-scale output current. r set is the reference resistor that determines the amplifier out- put current of the MAX5858A (figure 4). this current is mirrored into the current-source array where i fs is equally distributed between matched current segments and summed to valid output current readings for the dacs.
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ______________________________________________________________________________________ 19 pllen f2en f1en differential clock frequency f clkdiff (mhz) clock frequency f clk (mhz) dac rate f dac interpolation max signal bandwidth (mhz) 100 n/a (connect clxp low and clxn high) 0 to 165 (input) f clk 1x 82 101 n/a (connect clxp low and clxn high) 75 to 150 (input) 2 x f clk 2x 63 111 n/a (connect clxp low and clxn high) 37 to 75 (input) 4 x f clk 4x 31 0 0 0 0 to 165 f clkdiff (output) f clkdiff 1x 82 0 0 1 0 to 300 f clkdiff /2 (output) f clkdiff 2x 63 0 1 1 0 to 300 f clkdiff /4 (output) f clkdiff 4x 31 010 110 illegal table 5. pll clocking modes i fs 0.1 f 10 f av dd r set i ref refr av dd refo 1.24v bandgap reference current- source array external 1.24v reference ren MAX5858A max6520 agnd agnd agnd figure 5. MAX5858A with external reference external reference to disable the internal reference of the MAX5858A, con- nect ren to av dd . apply a temperature-stable, external reference to refo to set the full-scale output (figure 5). for improved accuracy and drift performance, choose a fixed output voltage reference such as the max6520 bandgap reference. detailed timing the MAX5858A accepts an input data rate up to 165mhz or the dac conversion rate of 300mhz. the input latches on the rising edge of the clock, whereas the output latches on the following rising edge.
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 20 ______________________________________________________________________________________ clkxn 1 clkxp 1 clk 2 t cxd t cxd t cwh t cws da0 da9/ control word db0 db9 da n da n+1 db n db n+1 control word t dcsr t dchr 1. clkxp and clkxn must be present when pll is disabled, with pllen connected to gnd. the diagram shows 4x interpolation. 2. clk is an output when pll is disabled with pllen connected to gnd, otherwise, it is an input. cw figure 6. timing diagram for noninterleave data mode (ide = low) figure 6 depicts the write cycle of the MAX5858A in 4x interpolation mode. with the interpolation feature enabled, the device can operate with the pll enabled or disabled. with the pll disabled (pllen = 0), the clock signal is applied to clkxp/clkxn and internally divided by 4 to generate the dac s clk signal. the clk signal is a divide-by-four output used to synchronize data into the MAX5858A data ports. the clkxp/clkxn signal dri- ves the interpolation filters and dac cores at the desired conversion rate. if the pll is enabled (pllen = 1), clk becomes an input and the clock signal is applied to clk. in figure 6, the clk signal is multiplied by a factor of four by the pll and distributed to the interpolation filters and dac cores. in this mode, clkxp must be pulled low and clkxn pulled high. the MAX5858A can operate with a single-ended clock input used as both data clock and conversion clock. to operate the device in this mode, disable the interpolation filters and enable the pll (pllen = 1). apply a single- ended clock input at clk. the clk signal acts as the data synchronization clock and dac core conversion clock. though the pll is enabled, the lock pin (lock) is not valid and the pll is internally disconnected from interpolating filters and dac cores. in this mode, clkxp must be pulled low and clkxn pulled high. figure 6 shows the timing for the control word write pulse ( cw ). an 8-bit control word routed through chan- nel a s data port programs the gain matching, interpo- lator configuration, and operational mode of the MAX5858A. the control word is latched on the falling edge of cw . the cw signal is asynchronous with con- version clocks clk and clkxn/clkxp; therefore, the conversion clock (clk or clkxn/clkxp) can run unin- terrupted when a control word is written to the device.
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ______________________________________________________________________________________ 21 the MAX5858A can operate in interleave data mode by setting ide = 1. in interleave data mode, data for both dac channels is written through input port a. channel b data is written on the falling edge of the clk signal and then channel a data is written on the following ris- ing edge of the clk signal. both dac outputs (channel a and b) are updated simultaneously on the next rising edge of clk. in interleave data mode, the maximum input data rate per channel is one-half the rate of nonin- terleave mode. interleave data mode is an attractive feature that lowers digital i/o pin count, reduces digital asic cost and improves system reliability (figure 7). applications information differential-to-single-ended conversion the MAX5858A exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order qam modulation with ofdm. figure 8 shows a typical application circuit with output transformers performing the required differential-to-sin- gle-ended signal conversion. in this configuration, the MAX5858A operates in differential mode, which reduces even-order harmonics, and increases the avail- able output power. da0 da9 10 MAX5858A 1/2 50 ? 100 ? 50 ? outpa outna v outa , single ended db0 db9 10 MAX5858A 1/2 50 ? 100 ? 50 ? outpb outnb v outb , single ended pv dd dv dd av dd pgnd dgnd agnd figure 8. application with output transformer performing differential to single-ended conversion clkxn 1 clkxp 1 clk 2 t cxd t cxd da0 da9 da n da n+2 db n+1 da n+1 db n+2 t dcsr t dcsf t dchf t dchr 1. clkxp and clkxn must be present when pll is disabled, with pllen connected to gnd. the diagram shows 4x interpolation. 2. clk is an output when pll is disabled with pllen connected to gnd, otherwise, it is an input. figure 7. timing diagram for interleave data mode (ide = high)
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 22 ______________________________________________________________________________________ differential dc-coupled configuration figure 9 shows the MAX5858A output operating in differ- ential, dc-coupled mode. this configuration can be used in communication systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed dac for i/q synthe- sis. in these applications, information bandwidth can extend from 10mhz down to several hundred kilohertz. dc-coupling is desirable in order to eliminate long dis- charge time constants that are problematic with large, expensive coupling capacitors. analog quadrature upconverters have a dc common-mode input require- ment of typically 0.7v to 1.0v. the MAX5858A differential i/q outputs can maintain the desired full-scale original level at the required 0.7v to 1.0v dc common-mode volt- age when powered from a single 2.85v (5%) supply. the MAX5858A meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks. power supplies, bypassing, decoupling, and layout grounding and power-supply decoupling strongly influ- ence the MAX5858A performance. unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. in addition, electro- magnetic interference (emi) can either couple into or be generated by the MAX5858A. observe the ground- ing and power-supply decoupling guidelines for high- speed, high-frequency applications. follow the power supply and filter configuration to achieve optimum dynamic performance. use of a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes is recommend- ed. run high-speed signals on lines directly above the ground plane. the MAX5858A has separate analog and digital ground buses (agnd, pgnd, and dgnd, respectively). provide separate analog, digital, and clock ground sections on the pc board with only one point connecting the three planes. the ground connec- tion points should be located underneath the device and connected to the exposed paddle. run digital sig- nals above the digital ground plane and analog/clock signals above the analog/clock ground plane. digital signals should be kept away from sensitive analog, clock, and reference inputs. keep digital signal paths short and metal trace lengths matched to avoid propa- gation delay and data skew mismatch. the MAX5858A includes three separate power-supply inputs: analog (av dd ), digital (dv dd ), and clock (pv dd ). use a single linear regulator power source to branch out to three separate power-supply lines (av dd , dv dd , pv dd ) and returns (agnd, dgnd, pgnd). filter each power-supply line to the respective return line using lc filters comprising ferrite beads and 10f capacitors. filter each supply input locally with 0.1f ceramic capacitors to the respective return lines. note: to maintain the dynamic performance of the electrical characteristics , ensure the voltage difference between dv dd , av dd , and pv dd does not exceed 150mv. thermal characteristics and packaging thermal resistance 48-lead tqfp-ep: ja = 27.6 c/w keep the device junction temperature below +125 c to meet specified electrical performance. lower the power-supply voltage to maintain specified perfor- mance when the dac update rate approaches 300msps and the ambient temperature equals +85 c. da0 da9 10 MAX5858A 1/2 1/2 50 ? 50 ? pv dd dv dd av dd pgnd dgnd agnd outpa outna db0 db9 10 MAX5858A 50 ? 50 ? outpb outnb figure 9. application with dc-coupled differential outputs
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll ______________________________________________________________________________________ 23 the MAX5858A is packaged in a 48-pin tqfp-ep pack- age, providing design flexibility, increased thermal effi- ciency, and optimized ac performance of the dac. the ep enables the implementation of grounding techniques, which are necessary to ensure highest performance operation. in this package, the data converter die is attached to an ep leadframe with the back of the frame exposed at the package bottom surface, facing the pc board side of the package. this allows a solid attachment of the package to the pc board with standard infrared (ir)- flow soldering techniques. a specially created land pat- tern on the pc board, matching the size of the ep, ensures the proper attachment and grounding of the dac. designing vias* into the land area and imple- menting large ground planes in the pc board design achieve optimal dac performance. use an array of 3 ? 3 (or greater) vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 48-pin tqfp- ep package. dynamic performance parameter definitions adjacent channel leakage ratio (aclr) commonly used in combination with wideband code- division multiple-access (wcdma), aclr reflects the leakage power ratio in db between the measured power within a channel relative to its adjacent channel. aclr provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited rf signal passes through a nonlinear device. total harmonic distortion (thd) thd is the ratio of the rms sum of all essential harmon- ics (within a nyquist window) of the input signal to the fundamental itself. this can be expressed as: where v 1 is the fundamental amplitude, and v 2 through v n are the amplitudes of the 2nd through nth-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal component) to the rms value of the next-largest spectral component. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in db fs with respect to the dac s full- scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. multitone power ratio (mtpr) a series of equally spaced tones are applied to the dac with one tone removed from the center of the range. mtpr is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequen- cies), which appears as the largest spur at the frequency of the missing tone in the sequence. this test can be per- formed with any number of input tones; however, four and eight tones are among the most common test conditions for cdma- and gsm/edge-type applications. intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc of either out- put tone to the worst 3rd-order (or higher) imd products. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. for a dac, the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification no more negative than -1 lsb guarantees monotonic transfer function. offset error offset error is the current flowing from positive dac output when the digital input code is set to zero. offset error is expressed in lsbs. thd v v v v v n = ++ + ? ? ? ? ? ? ? ? ? ? log ... ... / 20 2 2 3 2 4 22 1 * vias connect the land pattern to internal or external copper planes.
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll 24 ______________________________________________________________________________________ gain error a gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. the ideal current is defined by reference voltage at v refo / i ref x 32. settling time the settling time is the amount of time required from the start of a transition until the dac output settles to its new output value to within the converter s specified accuracy. glitch impulse a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011 111 to 100 000. this occurs due to timing variations between the bits. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impulse is usu- ally specified in pv-s. chip information transistor count: 178,376 process: cmos
MAX5858A dual, 10-bit, 300msps, dac with 4x/2x/1x interpolation filters and pll maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 48l,tqfp.eps

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